Scan testing is an important tool for efficiently testing complex integrated circuits, such as systems-on-a-chip (SOCs), during silicon debug and device production. Generally, scan cells, which typically are one-bit register elements including a multiplexer and a flip-flop, are associated with test-critical nodes of a corresponding circuit block. During normal operation of the chip, the scan flip-flops operate as part of the combinatorial logic as typical register elements. During scan mode, the scan cells of one or more circuit blocks are connected together through their multiplexers to form a scan chain. Each scan chain is essentially a shift register into which an input test vector is shifted serially with a clock signal. Once the scan chain is loaded with the test vector, the individual bits are presented in parallel to corresponding input nodes of the corresponding circuit block under test. Subsequently, a capture operation is performed, in which the resulting bits at corresponding output nodes of the circuit block are clocked in parallel into the scan cells of the scan chain. The resulting output test vector is then shifted out of the scan chain for observation and analysis.
One significant challenge to designing efficient scan chains is minimizing the amount of chip area required for their fabrication. One factor contributing to overall size of the scan elements are the multiplexers, briefly mentioned above. Generally, during normal mode operations, the multiplexer couples the scan cell flip-flop to its normal operating mode source of the corresponding circuit block. In scan mode, the multiplexer couples the scan cell flip-flop to the output of the previous scan cell in the corresponding scan chain. The multiplexer is typically controlled by a scan enable signal, which controls all the multiplexers of the corresponding scan chain, and often, all the multiplexers of all the scan chains on the integrated circuit.
Another significant factor in the design of scan chains is the amount and complexity of the interconnect required to link the scan cells together to form scan chains. Furthermore, some consideration to signal timing is required in scan chain designs, since the multiplexers introduce a small amount of additional signal delay in the operational path.
The chip area, as well as the amount and complexity of the interconnect, required for scan chain fabrication can be significant in complex integrated circuits utilizing thousands of scan cells. While minimizing chip area and interconnections are significant factors in almost any integrated circuit design, these factors nonetheless must be balanced with the competing need to provide scan testing for a sufficient number of critical circuit nodes to insure proper operation of the individual circuit blocks.
Hence new techniques are required for implementing scan testing during the development and production of complex integrated circuits. These techniques should minimize chip area and still provide the requisite number of scan cells on chip necessary to observe each of the critical circuit nodes.